Ming Chen.

Research

An environment-aware PUF key generator for post-quantum cryptography

PUFs let a chip avoid storing private keys in memory, which makes them a natural root of trust for post-quantum cryptography. Ring-oscillator PUFs on FPGAs, however, drift with temperature and voltage, and the usual fix, a BCH error-correcting code, eats logic. This work senses die temperature and voltage with the on-chip XADC and compensates through a carry-chain delay line, so a lightweight repetition code can replace BCH; SHAKE-256 then derives the 512-bit ML-KEM seed.

Undergraduate researchNSTC undergraduate grantVerilog · Nexys A7-100T (Xilinx Artix-7 XC7A100T) · Vivado
Read the proposal (PDF)

01

How a key grows out of the chip

When temperature or voltage moves, a lookup table retunes the delay line so the PUF's fingerprint stays stable; SHAKE-256 then derives the ML-KEM seed.

XADCDie temperature · voltage
Calibration table4096×8 BRAM
delay_ctrlWith hysteresis
Tunable RO-PUFCARRY4 carry-chain delay
Repetition codeHelper-data reconstruction
LEARNSweep 0–255, keep min HD
TRNGSP 800-90B health tests
ML-KEM seed512-bit (d‖z)
SHAKE-256Key derivation

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Undergraduate research

Implementation and measurements

Verilog on a Nexys A7-100T; figures from the research progress report.

mean Hamming distance on stable bits (31-vote enrollment + unstable-pair mask)
0.03 / 128
mean Hamming distance on stable bits (31-vote enrollment + unstable-pair mask)
bit-error rate (2¹⁷-cycle counting window)
0.008%
bit-error rate (2¹⁷-cycle counting window)
keys reproduced across a 40–50 °C heater sweep
250 / 250
keys reproduced across a 40–50 °C heater sweep
LUTs vs a BCH(127,64) decoder at 128 pairs (−58.7% at 254 pairs)
−70.5%
LUTs vs a BCH(127,64) decoder at 128 pairs (−58.7% at 254 pairs)
NIST SP 800-22 tests passed by the TRNG output
15 / 15
NIST SP 800-22 tests passed by the TRNG output

NSTC undergraduate grant

Research proposal

Design of a High-Stability PUF-Based Post-Quantum Key Generation System Based on FPGA XADC Environmental Sensing Mechanism

  1. 01Step 1Tunable RO-PUF on CARRY4
  2. 02Step 2Build the D_opt = f(T, V) table
  3. 03Step 3XADC DRP + FSM + hysteresis
  4. 04Step 4SHAKE-256 → ML-KEM seed, LUTs vs BCH

Proposal targets

  • Bit-error rate from above 5% to below 3%
  • At least 30% fewer slice LUTs than PUF + BCH(127,64)
  • Pass all 15 NIST SP 800-22 tests
Read the proposal (PDF)
System architecture
System architecture
Fraction of response bits equal to 1 versus the A-side delay code (128 pairs, die at about 40 °C)
Fraction of response bits equal to 1 versus the A-side delay code (128 pairs, die at about 40 °C)
Intra-device BER versus counting window per pair (die at 40.4 °C)
Intra-device BER versus counting window per pair (die at 40.4 °C)
On-chip heater: open-loop steps of 8 and 16 banks, then closed-loop regulation at two set-points and a cool-down
On-chip heater: open-loop steps of 8 and 16 banks, then closed-loop regulation at two set-points and a cool-down
Mean HD (of 128 bits) versus die temperature, 50 samples per point
Mean HD (of 128 bits) versus die temperature, 50 samples per point

Current limitations

  • The on-chip heater's range is too narrow to exercise the compensation.
  • The carry-chain RO limits the array to roughly 250–380 pairs on this device.
  • Vivado cannot lock RO routing across rebuilds.

Next steps

  1. 01Chamber tests over 20–75 °C to quantify the compensation
  2. 02SP 800-90B evaluation of the raw entropy source
  3. 03Integrate an ML-KEM core and verify with FIPS 203 vectors
  4. 04A smaller RO cell to reach the 256-bit entropy budget
  5. 05Uniqueness measurements across multiple boards